AD9773 12-Bit, 160 MSPS, 2×/4×/8× Interpolating Dual TxDAC D/A Converter

●GENERAL DESCRIPTION
■The AD9773¹ is the 12-bit member of the AD977x pin-compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+® family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options. These options include selectable 2×/4×/8× interpolation filters; fS/2, fS/4, or fS/8 digital quadrature modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a single-port or dual-port data interface.
■The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family’s pass-band noise/distortion performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and side-band suppression errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC.
■The AD9773 features the ability to perform fS/2, fS/4, and fS/8 digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9773 accepts I and Q complex data (representing a single or multi-carrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (for example, the direct IF mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate.
■The AD977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. An internal programmable divider simplifies clock generation in the converter when using an external clock source. A flexible data input interface allows for straight binary or twos complement formats and supports single-port interleaved or dual-port data.
■Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. The AD9773 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power.
■Targeted at a wide dynamic range, multicarrier, and multi-standard systems, the superb baseband performance of the AD9773 is ideal for wide band CDMA, multicarrier CDMA, multicarrier TDMA, multicarrier GSM, and high performance systems employing high order QAM modulation schemes. The image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems.
●FEATURES
■12-bit resolution, 160 MSPS/400 MSPS
▲input/output data rate
■Selectable 2×/4×/8× interpolating filter
■Programmable channel gain and offset adjustment
■f-S/2, f-S/4, f-S/8 digital quadrature modulation capability
■Direct IF transmission mode for 70 MHz + IFs
■Enables image rejection architecture
■Fully compatible SPI port
■Excellent ac performance
▲SFDR−69 dBc @ 2 MHz to 35 MHz
▲WCDMA ACPR −69 dB @ IF = 19.2 MHz
■Internal PLL clock multiplier
■Selectable internal clock divider
■Versatile clock input
▲Differential/single-ended sine wave or
◆TTL/CMOS/LVPECL compatible
■Versatile input data interface
▲Twos complement/straight binary data coding
▲Dual-port or single-port interleaved input data
■Single 3.3 V supply operation
■Power dissipation: typical 1.2 W @ 3.3 V
■On-chip 1.2 V reference
■80-lead thin quad flat package, exposed pad (TQFP_EP)